PART |
Description |
Maker |
UPD44165084 UPD44165084F5-E60-EQ1 UPD44165364F5-E6 |
18M-BIT QDRII SRAM 4-WORD BURST OPERATION 1800万位推出QDRII SRAM4个字爆发运作 18M-BIT QDRII SRAM 4-WORD BURST OPERATION 1800万位推出QDRII SRAM个字爆发运作
|
NEC Corp. NEC, Corp.
|
PD46185092BF1-E40-EQ1 PD46185182BF1-E40-EQ1 PD4618 |
18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
|
Renesas Electronics Corporation
|
UPD44164084F5-E40-EQ1 UPD44164364F5-E50-EQ1 |
18M-BIT DDRII SRAM 4-WORD BURST OPERATION 1800万位的SRAM 4条DDRII字爆发运
|
NEC, Corp.
|
UPD44164365F5-E50-EQ1 |
18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION 1800万位条DDRII SRAM的分离I / O 2字爆发运
|
NEC, Corp.
|
CY7C1511V18-250BZC CY7C1511V18-167BZC |
72-Mbit QDRII SRAM 4-Word Burst Architecture 8M X 8 QDR SRAM, 0.5 ns, PBGA165
|
Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
|
CY7C1314BV18-167BZXC |
18-Mbit QDRII SRAM 2 Word Burst Architecture 512K X 36 QDR SRAM, 0.5 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
CY7C1165V18 CY7C1163V18 CY7C1161V18 CY7C1176V18 CY |
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 9 QDR SRAM, 0.45 ns, PBGA165 18-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 18兆位的国防评估报告⑩- II SRAM字突发架构(2.5周期读写延迟 18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
|
CY7C1565V18-300BZI |
72-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 36 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
CY7C1512KV18-250BZIT |
72-Mbit QDRII SRAM Two-Word Burst Architecture
|
Cypress
|
CYPT1543AV18-250GCMB CYPT1545AV18-250GCMB CYRS1543 |
72-Mbit QDRII SRAM Four-Word Burst Architecture with RadStop™ Technology
|
Cypress
|
CY7C2263XV18-633BZXC CY7C2263XV18-600BZXC CY7C2265 |
36-Mbit QDRII Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
Cypress
|
CY7C1263XV18 CY7C1265XV18-633BZXC CY7C1263XV18-600 |
36-Mbit QDR? II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDRII Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor
|